


The Wafer Alignment department develops software that enables chipmakers to position patterns on wafers with extreme precision. Your work as a Computer Science internship: performance optimization student helps us improve the speed and efficiency of these models. These models are central to the scanner’s performance and must deliver nanometer‑level accuracy. Increasing model complexity brings better precision but also adds resource usage and calculation time. In this internship, you help explore solutions to optimize this balance and support overall system throughput. You will analyze the current software performance of Wafer Alignment models and explore ways to optimize them. You will also create and test a prototype to validate the selected improvements. Throughout the Computer Science internship: performance optimization, you collaborate closely with engineers from different disciplines.