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Paid Internship
Work Mode
Time Spent
Required Degree
Duration

8Open Positions

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Design Verification Engineer Intern

Analog Devices
Found 1 month ago
Location
Valencia, Spain
Time
Not disclosed
Work Mode
Not disclosed
Salary
Not disclosed
Visa Help
Not disclosed
Last Verified
1 month ago

Education

  • Bachelor
  • Master

Skills & Qualifications

Technical Skills

  • SystemVerilog/UVM
  • Verilog
  • VHDL
  • Python
  • Perl
  • Shell

Soft Skills

  • analytical skills
  • problem-solving skills
  • communication
  • teamwork

Job Description

Assist in developing and maintaining verification environments using SystemVerilog/UVM. Run simulations and analyze results to identify and debug functional issues. Support regression testing and coverage analysis. Collaborate with design and verification teams to understand specifications and contribute to test planning. Document verification results and contribute to reviews.

Requirements

  • Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Familiarity with digital design concepts and hardware description languages (e.g., Verilog, VHDL).
  • Exposure to scripting languages (e.g., Python, Perl, Shell)
  • Strong analytical and problem-solving skills.
  • Excellent communication and teamwork abilities.

Related Field

  • Software Engineering

Related Subfield

  • Software QA & Testing

Languages

  • English

Nice to Haves

  • digital design concepts
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