

Power integrity and signal integrity simulations become increasingly important with smaller technology nodes in system-on-chip electronic designs. Abstracted simulation models are needed, which still deliver realistic response on analog-like current demand patterns. In this work the limits of existing modeling and simulation methods for power integrity and signal integrity depending on modeling methods and feasible simulation complexity should be investigated and stretched out. How far is the idea of a “digital twin” simulation combining electrical, electro-thermal, and electro-magnetic effects already feasible in SoC design?